Atomic-Scale Quantum Computing Breakthrough: Transistors Could Shrink Below 4 Nanometers

Atomic-Scale Quantum Computing Breakthrough: Transistors Could Shrink Below 4 Nanometers

A research team at the Korea Advanced Institute of Science and Technology (KAIST) has developed a simulation-based method capable of predicting how small future transistors can be scaled before quantum effects begin to interfere with their operation. The breakthrough could help engineers design next-generation semiconductor chips more efficiently.

The team employed atomic-scale quantum mechanical calculations to identify the scaling limits of transistors — the tiny switches inside electronic devices that control the flow of electric current. Their findings could enable chipmakers to continue shrinking transistors beyond current technology nodes while reducing the need for costly trial-and-error experimentation during development.

As the semiconductor industry pushes into what is commonly referred to as the "2-nanometer era," the actual physical dimensions of transistors remain significantly larger than 2 nm. One of the key barriers to further miniaturization is quantum tunneling — a phenomenon in which electrons pass through barriers that should theoretically block them, making precise current control increasingly difficult.

In the past, identifying this physical limit has been extremely challenging, as it is nearly impossible to directly measure the atomic-scale interactions occurring at the junction between metal contacts and semiconductor channels.

Searching for the Atomic-Scale Limit

To overcome this challenge, the KAIST team employed first-principles calculations — a computational approach that predicts material behavior directly from the laws of physics, without relying on experimental data.

Building on a previously developed framework called Multi-Space Constrained-Search Density Functional Theory (MS-DFT), the researchers conducted virtual transfer length method (TLM) experiments — a standard technique used to measure contact resistance between metal electrodes and semiconductor materials.

Through simulation, the team was able to examine how electrons move across metal-semiconductor interfaces and determine the critical tunneling length — the threshold at which electron leakage begins to degrade transistor performance.

The researchers applied this method to monolayer molybdenum disulfide (MoS₂), a two-dimensional semiconductor material. Because it can be fabricated at atomic-layer thickness, MoS₂ is considered a highly promising candidate for future transistor channels.

The analysis revealed that the extent to which electrons penetrate the channel varies depending on the choice of metal electrode and the atomic structure of the contact interface. As a result, the minimum achievable transistor size is not a fixed value — it depends on material selection and device design.

Pushing Beyond Existing Technology Nodes

According to the study, the critical tunneling length changes with the metal's work function and the geometry of the contact structure. This means engineers may be able to tune the scaling limit of a transistor by selecting different materials and interface configurations.

Among the various combinations studied, the team found that electron leakage could be suppressed at sizes below 4 nanometers, suggesting that future transistors may be scalable beyond what current technology allows.

The researchers also proposed a design strategy combining two-dimensional semiconductors with different properties to reduce power consumption in future chips.

"The significance of this study lies in the fact that it presents a new physical criterion for defining how small next-generation transistors can be," said Professor Yong-Hoon Kim of KAIST.

"By computationally analyzing quantum mechanical phenomena in the sub-10-nanometer regime that are difficult to probe experimentally, we have opened a new pathway for applying these findings to next-generation transistor design."

The research team believes this approach could provide chip designers with a platform for predicting transistor performance and scaling limits before fabrication begins, potentially shortening development cycles for future AI and high-performance computing chips.

The study has been published in the international journal npj Computational Materials.

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